Weifang University, 261061 Weifang, China

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Abstract—This design using FPGA parallel architecture, high computing speed and high-speed reliability of USB2.0 interface, designed an FPGA + USB2.0 + computer FIR digital filter system, organically combining the speed of FPGA and flexibility of Computer through USB2.0 bus. The results demonstrated that the coefficients configuring of the system is easy, which can adjust the filter coefficients flexibly according to the actual demand, that it can effectively filter out the noise signals.

Index Terms—finite impulse response digital filter, reconfigurable coefficient, hardware design

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Cite: Guosheng Xu, " The Hardware Design of Parameter-Adjustable FIR Filter System," Journal of Computers vol. 8, no. 5, pp. 1371-1375, 2013.