JCP 2008 Vol.3(4): 31-38 ISSN: 1796-203X
doi: 10.4304/jcp.3.4.31-38
doi: 10.4304/jcp.3.4.31-38
Implementation of CMOS Low-power Integer-N Frequency Synthesizer for SOC Design
Debashis Mandal, T. K. Bhattacharyya
Abstract—The paper reports the implementation of a frequency synthesizer for system-on-chip (SOC) design. The epi-digital CMOS process is used to provide SOC solution. This work focuses on low-power consumption to achieve longer life-time of batteries. A 2.4GHz frequency synthesizer has been fabricated in 0.18μm epi-digital CMOS technology for ZigBee applications, which consumed 7.95mW from 1.8V supply. The synthesizer has achieved phase-noise of −81.55dBc/Hz and −108.55dBc/Hz at 100kHz and 1MHz offset, respectively. The settling time measured is less than 25μs for an output frequency change of 75MHz from 2.4GHz. The chip core area is 0.75 × 0.65mm2.
Index Terms—Frequency synthesizers, phase locked loops (PLLs), oscillators, integer-N topology, ZigBee standards, system-on-chip solution, low-power design.
Cite: Debashis Mandal, T. K. Bhattacharyya, "Implementation of CMOS Low-power Integer-N Frequency Synthesizer for SOC Design," Journal of Computers vol. 3, no. 4, pp. 31-38, 2008.
General Information
ISSN: 1796-203X
Abbreviated Title: J.Comput.
Frequency: Bimonthly
Abbreviated Title: J.Comput.
Frequency: Bimonthly
Editor-in-Chief: Prof. Liansheng Tan
Executive Editor: Ms. Nina Lee
Abstracting/ Indexing: DBLP, EBSCO, ProQuest, INSPEC, ULRICH's Periodicals Directory, WorldCat,etc
E-mail: jcp@iap.org
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