Volume 3 Number 4 (Apr. 2008)
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JCP 2008 Vol.3(4): 39-49 ISSN: 1796-203X
doi: 10.4304/jcp.3.4.39-49

Leakage Controlled Read Stable Static Random Access Memories

Sayeed A. Badrudduza, Ziyan Wang, Giby Samson, Lawrence T. Clark
1Arizona State University, Tempe, AZ, USA

Abstract—Semiconductor manufacturing process scaling increases leakage and transistor variations, both of which are problematic for static random access memory (SRAM). Since SRAM is a critical component in modern CMOS integrated circuits, novel approaches to addressing these problems are needed. Here, six and seven transistor SRAM cells are presented that do not suffer from reduced stability when read. The cells reside in a low leakage, voltage collapsed, low standby power mode when not being accessed. Both six transistor and seven transistor variations of the basic approach are explored through simulation and measured results. The circuit topology, layout, and impact on memory design of the proposed cell designs are described. Measured results on a 130 nm foundry fabrication process demonstrate the viability of three of the possible cell configurations. Circuit simulation is used to explore the cell stability in the presence of process variations, and to show the value of the proposed SRAM cell designs on future scaled manufacturing technologies.

Index Terms—SRAM, static noise margin, reverse body bias, leakage reduction

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Cite: Sayeed A. Badrudduza, Ziyan Wang, Giby Samson, Lawrence T. Clark, "Leakage Controlled Read Stable Static Random Access Memories," Journal of Computers vol. 3, no. 4, pp. 39-49, 2008.

General Information

ISSN: 1796-203X
Abbreviated Title: J.Comput.
Frequency: Monthly
Editor-in-Chief: Prof. Liansheng Tan
Executive Editor: Ms. Nina Lee
Abstracting/ Indexing: DBLP, EBSCO,  ProQuest, INSPEC, ULRICH's Periodicals Directory, WorldCat, CNKI,etc
E-mail: jcp@iap.org
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