Beijing University of Technology, Embedded Software and System Institution Beijing 100022 China

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Abstract—Most high performance computing systems are large-scale computing systems, and consist tens of thousands computing nodes with superior capabilities. FPGAs are able to accelerate large scope and complicated computing with flexible configurations. More and more companies and research institutions integrate multi-FPGAs into high performance computing systems to get a better trade-off between high-performance and low power. How to design an effective topology for these integrated multi-FPGAs according different applications has become a key problem in this area. Acluster based architectureand corresponding partitioning approach are proposed in this paper. The proposed hierarchical topology taking full advantages of both traditional metallic lines and emerging interconnections to implement one-hop local communication within the cluster and one-hop global high-speed communication between clusters. The case study proved that the proposed architecture and partitioning approach can implement the fast mapping from the design to real computing system with multi-FPGAs, and accelerate the realization of high performance reconfigurable computing systems.

Index Terms—High performance computing, multi-FPGA architecture, FPGA partitioning, emerging interconnections

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Cite: Chunhua Xiao, Zhangqin Huang, Da Li, "A Cluster-based Hierarchical Partitioning Approach for Multiple FPGAs," Journal of Computers vol. 9, no. 9, pp. 2173-2180, 2014.