JCP 2010 Vol.5(10): 1478-1485 ISSN: 1796-203X
doi: 10.4304/jcp.5.10.1478-1485
doi: 10.4304/jcp.5.10.1478-1485
Pseudorandom Direct Sampler for Non-Uniform Sub-sampling Architecture in a Multistandard Receiver
Asma Maalej1, 2, Manel Ben-Romdhane1, Chiheb Rebai1, Patricia Desgreys2, Patrick Loumeau,2 and Adel Ghazel1
1 Asma Maalej, Manel Ben-Romdhane, Chiheb Rebai, Patricia Desgreys, Patrick Loumeau, and Adel Ghazel
2 LTCI-CNRS UMR 5141, Telecom ParisTech, France
Abstract—In this paper, a Non-Uniform Sampling (NUS) technique for down-conversion stage in a multistandard radio receiver is proposed. For both narrowband and wideband standard processing, NUS promises relaxing system design constraints, decreasing the sampling frequency as well as reducing power consumption. A non-uniform clock generator, called Pseudorandom Direct Sampler (PDS), is described. PDS is used to non-uniformly control the Analog-to-Digital Converter (ADC) performing IF sub-sampling in proposed GSM/UMTS/WiFi multistandard receiver architecture. PDS architecture is based on using modified Direct Digital Synthesizer (DDS) including pseudorandom behavior. A 90- nm CMOS FPGA based prototype of PDS reveals an internal clocking up to 350 MHz and a power consumption lower than 4 mW.
Index Terms—Multistandard receiver, Non-Uniform Sampling, Sub-sampling, Direct Digital Synthesizer
2 LTCI-CNRS UMR 5141, Telecom ParisTech, France
Abstract—In this paper, a Non-Uniform Sampling (NUS) technique for down-conversion stage in a multistandard radio receiver is proposed. For both narrowband and wideband standard processing, NUS promises relaxing system design constraints, decreasing the sampling frequency as well as reducing power consumption. A non-uniform clock generator, called Pseudorandom Direct Sampler (PDS), is described. PDS is used to non-uniformly control the Analog-to-Digital Converter (ADC) performing IF sub-sampling in proposed GSM/UMTS/WiFi multistandard receiver architecture. PDS architecture is based on using modified Direct Digital Synthesizer (DDS) including pseudorandom behavior. A 90- nm CMOS FPGA based prototype of PDS reveals an internal clocking up to 350 MHz and a power consumption lower than 4 mW.
Index Terms—Multistandard receiver, Non-Uniform Sampling, Sub-sampling, Direct Digital Synthesizer
Cite: Asma Maalej, Manel Ben-Romdhane, Chiheb Rebai, Patricia Desgreys, Patrick Loumeau, and Adel Ghazel, " Pseudorandom Direct Sampler for Non-Uniform Sub-sampling Architecture in a Multistandard Receiver," Journal of Computers vol. 5, no. 10, pp. 1478-1485, 2010.
General Information
ISSN: 1796-203X
Abbreviated Title: J.Comput.
Frequency: Bimonthly
Abbreviated Title: J.Comput.
Frequency: Bimonthly
Editor-in-Chief: Prof. Liansheng Tan
Executive Editor: Ms. Nina Lee
Abstracting/ Indexing: DBLP, EBSCO, ProQuest, INSPEC, ULRICH's Periodicals Directory, WorldCat,etc
E-mail: jcp@iap.org
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