Deptt. Of Electronics Engineering, Aligarh Muslim University, Aligarh, India

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Abstract—This paper present new energy efficient methods of designing switches and routing interconnects inside FPGA using novel variants of Dynamic Threshold MOS (DTMOS) instead of traditional NMOS pass transistor based switches and interconnects. The extra needed transistors can be easily shared, in multiplexer based routing architecture of FPGA, keeping area overhead to be minimum. Extensive transistor level HSPICE simulation based on Berkeley Predictive Technology Model (BPTM) for 65nm device at operating frequency of 300MHz shows an average 23.35% improvement in power delay product (PDP) of simple switch (NMOS pass transistor) and an average 32.83% improvement in the PDP of Virtex-II FPGA routing interconnects over conventional approaches. Since FPGA consists of thousands of Multiplexer based routing interconnects, hence the overall improvement in the PDP is significant.

Index Terms—Low power, High speed, Dynamic threshold-CMOS, FPGA -switches, interconnects.

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Cite: Kureshi A.K., Mohd. Hasan, "DTMOS Based Low Power High Speed Interconnects for FPGA," Journal of Computers vol. 4, no. 10, pp. 921-926, 2009.