¹Politecnico di Torino/Dipartimento di Automatica e Informatica, Torino, Italy

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Abstract—SRAM-based Field Programmable Gate Arrays (FPGAs) are very susceptible to Single Event Upsets (SEUs) that may have dramatic effects on the circuits they implement. In this paper we present a design flow composed by both standard tools, and ad-hoc developed tools, which designers can use fruitfully for developing circuits resilient to SEUs. Experiments are reported on both benchmarks circuits and on a realistic circuit to show the capabilities of the proposed design flow.

Index Terms—FPGA, SEU, fault tolerance

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Cite: L. Sterpone, M. Violante, "Hardening FPGA-based systems against SEUs: A new design methodology," Journal of Computers vol. 1, no.1, pp. 22-30 , 2006.