Volume 7 Number 10 (Oct. 2012)
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JCP 2012 Vol.7(10): 2446-2453 ISSN: 1796-203X
doi: 10.4304/jcp.7.10.2446-2453

A Redundant FPGA Based Controller for Subsea Blowout Preventer Stack

Zengkai Liu, Yonghong Liu, Baoping Cai, Fei Wang, Zhili Chen, Xiaojie Tian, Yazhou Wang
College of Mechanical and Electronic, China University of Petroleum, Qingdao, China
Abstract—A redundant Field Programmable Gate Array (FPGA) based controller for subsea Blowout Preventer (BOP) is presented. Triple modular redundancy technique is used for architecture design, since high reliability is a necessary requirement for subsea BOP control system. A multiprocessor system is developed to enhance reliability of the processors and performance of the system. In addition, the shared memory method is applied to interchange information between the processors. One processor is responsible for communication, while the others run application programs. The proposed system has been implemented using three FPGA development boards, which are connected to each other through RS-232 serial ports. Besides, the voting algorithms for discrete input, analog input and discrete output are proposed. Functional simulation of the output voting is performed by using the Quartus II Simulator software. The results demonstrate that the proposed controller is able to tolerate faults, which means it has extremely high reliability.

Index Terms—FPGA, TMR, multiprocessor system, voting algorithm, subsea blowout preventer.

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Cite: Zengkai Liu, Yonghong Liu, Baoping Cai, Fei Wang, Zhili Chen, Xiaojie Tian, Yazhou Wang, "A Redundant FPGA Based Controller for Subsea Blowout Preventer Stack," Journal of Computers vol. 7, no. 10, pp. 2446-2453, 2012.

General Information

ISSN: 1796-203X
Abbreviated Title: J.Comput.
Frequency: Bimonthly
Editor-in-Chief: Prof. Liansheng Tan
Executive Editor: Ms. Nina Lee
Abstracting/ Indexing: DBLP, EBSCO,  ProQuest, INSPEC, ULRICH's Periodicals Directory, WorldCat,etc
E-mail: jcp@iap.org
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