¹ U.S. Army Engineer Research and Development Center, Vicksburg, MS, USA
² Jackson State University/Computer Engineering Department, Jackson, MS, USA

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Abstract—Contemporary field programmable gate arrays (FPGAs) combine the fine-grained design capability of the traditional lookup table with the speed of medium-scale and large-scale logic components such as RAM blocks or DSP blocks to provide for significant computational capability from a single FPGA. High performance reconfigurable computers, which typically use FPGAs as computational elements, have been commercially used to accelerate computational kernels. However, the deep pipelines and extensive parallelism needed for FPGAs to compete with GHz-scale general purpose processors make mapping of floating-point kernels a challenging research area. In this paper, we describe some of the progress that has been made towards solving some of these mapping challenges.

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Cite: Gerald R. Morris and Khalid H. Abed, " Mapping Floating-Point Kernels onto High Performance Reconfigurable Computers," Journal of Computers vol. 8, no. 4, pp. 859-873, 2013.