Volume 9 Number 7 (Jul. 2014)
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JCP 2014 Vol.9(7): 1639-1647 ISSN: 1796-203X
doi: 10.4304/jcp.9.7.1639-1647

Design of Frequency Tracking Loop for Satellite-Based AIS

Shexiang Ma, Yaping Feng
Key Laboratory of Computer Vision and System, Ministry of Education, Tianjin Key Laboratory of Intelligence Coputing and Novel Software Technology, Tianjin University of Technology, Tianjin 300384, China

Abstract—Due to a wide range of Doppler frequency shift and low SNR existing in the AIS transmission, it is difficult to decode correctly in Satellite-based AIS receiver. In order to solve the problem, a new design of PLL is proposed based on the theory of conventional PLL. The new design is aided by ML estimating. In the algorithm, frequency offsets are reduced to the fast capture zone after compensations to received AIS signals and then the phase locked loop start to track surplus frequency offsets. The simulation results indicate that the algorithm requiring the symbol number of fast capture is less than 256(the number of AIS frame symbols) when the SNR is 1dB and tracking precision is within 2 Hz. And it can be used under conditions of low SNR with large frequency offsets.

Index Terms—Satellite-based AIS; Doppler frequency shifts; low SNR; phase locked loop

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Cite: Shexiang Ma, Yaping Feng, "Design of Frequency Tracking Loop for Satellite-Based AIS," Journal of Computers vol. 9, no. 7, pp. 1639-1647, 2014.

General Information

ISSN: 1796-203X
Abbreviated Title: J.Comput.
Frequency: Bimonthly
Editor-in-Chief: Prof. Liansheng Tan
Executive Editor: Ms. Nina Lee
Abstracting/ Indexing: DBLP, EBSCO,  ProQuest, INSPEC, ULRICH's Periodicals Directory, WorldCat,etc
E-mail: jcp@iap.org
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