CTO, QSigma, Inc., Sunnyvale, CA 94089, USA, US Citizen.

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Abstract—This paper introduces Simultaneous Multi-Processor (SMP) cores. These SMP cores offer a high performance, efficient application target for the embedded system developer. SMP cores can be reprogrammed like a microprocessor in response to application requirement changes. They do not require caching, or superscalar instruction processing, greatly reducing silicon size and energy consumption. Also the power to any unused resources is gated off each clock cycle. This new class of instruction processors is discussed and shown through a core architecture implementing multiple simultaneous processes. This approach solves an inherent problem in VLIW instruction processing, giving the advantages of VLIW, while dramatically reducing instruction memories, and eliminating the need for instruction caching. Examples are given of the simultaneous processes of multiple threads. Merging these processes is shown. The SMP cores achieve the effect of superscalar instruction processing and multi-thread control, through a compile time procedure, without any additional hardware.

Index Terms—Caches, embedded controllers, SOC, superscalar microprocessors.

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Cite: Earle Jennings, "Simultaneous Multi-processor Cores for Efficient Embedded Applications," Journal of Computers vol. 13, no. 4, pp. 371-382, 2018.