Volume 3 Number 2 (Feb. 2008)
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JCP 2008 Vol.3(2): 48-54 ISSN: 1796-203X
doi: 10.4304/jcp.3.2.48-54

Low-Power and High-Performance 1-Bit CMOS Full-Adder Cell

Keivan Navi1, Omid Kavehei1, Mahnoush Ruholamini2, Amir Sahafi2, Shima Mehrabi2, Nooshin Dadkhahi2
1Shahid Beheshti University, Tehran, Iran
2Mahnoush Ruholamini, Amir Sahafi, Shima Mehrabi and Nooshin Dadkhahi

Abstract—In this paper a new low power and high performance adder cell using a new design style called “Bridge” is proposed. The bridge design style enjoys a high degree of regularity, higher density than conventional CMOS design style as well as lower power consumption, by using some transistors, named bridge transistors. Simulation results illustrate the superiority of the resulting proposed adder against conventional CMOS 1-bit full-adder in terms of power, delay and PDP. We have performed simulations using HSPICE in a 90 nanometer (nm) standard CMOS technology at room temperature; with supply voltage variation from 0.65v to 1.5v with 0.05v steps.

Index Terms—CMOS Circuit, VLSI, Full adder, Bridge style

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Cite: Keivan Navi, Omid Kavehei, Mahnoush Ruholamini, Amir Sahafi, Shima Mehrabi, Nooshin Dadkhahi, "Low-Power and High-Performance 1-Bit CMOS Full-Adder Cell," Journal of Computers vol. 3, no. 2, pp. 48-54, 2008.

General Information

ISSN: 1796-203X
Abbreviated Title: J.Comput.
Frequency: Bimonthly
Editor-in-Chief: Prof. Liansheng Tan
Executive Editor: Ms. Nina Lee
Abstracting/ Indexing: DBLP, EBSCO,  ProQuest, INSPEC, ULRICH's Periodicals Directory, WorldCat,etc
E-mail: jcp@iap.org
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