¹Deblina Sarkar1, Deepanjan Datta2 and S.Dasgupta
²School of Electrical and Computer Engineering, Purdue University, Purdue, Indiana, USA
³Department of Electronics and Computer Engineering, Indian Institute of Technology, Roorkee, India

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Abstract—Double-Gate (DG) MOSFET has emerged as one of the most promising devices for logic and memory circuit design in sub 10nm regime. In this paper, we investigate the gate-to-channel leakage, EDT, BTBT and sub-threshold leakage for DG MOSFET. Simulations are performed using 2D Poisson-Schrödinger simulator with tight-binding Green’s function approach. Then we analyze the effect of parameter variation to optimize low leakage SRAM cell using DG devices. The DG device/circuit co-design successfully demonstrates the benefit of using metal gate intrinsic body DG devices which significantly reduces BTBT and EDT in SRAM architecture.

Index Terms—Double-Gate, BTBT, sub-threshold, leakage, SRAM

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Cite: Deblina Sarkar, Deepanjan Datta and S.Dasgupta, "Modeling of Leakage Current Mechanisms in Nanoscale DG MOSFET and its Application to Low Power SRAM Design," Journal of Computers vol. 3, no. 2, pp. 37-47, 2008.