Department of Electronic Engineering, Tsinghua University, Beijing, China

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Abstract—The era of multi-core processor has come with the development of semiconductor technology, and heterogeneous multi-core processor is better than homogeneous one for both performance and power. In such circumstance, an efficient design methodology for such heterogeneous multi-core processor is given in this paper. At the simulator level, parallelized simulator is used to obtain the high simulation speed and conflict detection ability, at the RTL level, the common register file-based instruction set extension architecture is taken to speedup the application in multi-core systems. And simulation results at the RTLlevel show that with such design methodology, taking JPEG encoding as a case study, the heterogeneous multi-core designed gains 5.44X speedup than homogeneous one and the energy cost is only 22.9%of the homogeneous one. What’s more, the extra hardware logic cost is less than 25% compared with the homogeneous one, taking both the hardware logic cost and the performance into consideration, such methodology is better than popular XTensa for such architecture exploration based on instruction set extension.

Index Terms—heterogeneous multi-core, JPEG encoder, instruction set extension

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Cite: Bingbing Xia, Fei Qiao, Huazhong Yang, and Hui Wang, " Design Methodology of the Heterogeneous Multi-core Processor With the Combination of Parallelized Multi-core Simulator and Common Register File-Based Instruction Set Extension Architecture," Journal of Computers vol. 8, no. 2, pp. 356-364, 2013.