^{State Key Laboratory of Fluid Power Transmission and Control, Zhejiang University, Hangzhou, China}

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Abstract—This paper proposes a System-on-Programmable- Chip (SoPC) architecture to implement a stereo matching algorithm based on the sum of absolute differences (SAD) in a FPGA chip which can provide 1396×1110 disparity maps at 30 fps speed. The hardware implementation involves a 32- bit Nios II microprocessor, memory interfaces and stereo matching algorithm circuit module. The stereo matching algorithm core is modeled by the Matlab-based DSP Builder. The system can process many different sizes of stereo pair images through a configuration interface. The maximum horizon resolution of stereo images is 2048.

Index Terms—Stereo matching, System-on-programmablechip, FPGA, Disparity map, SAD, DSP Builder

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Cite: Xiang Zhang, Zhangwei Chen, "A FPGA Stereo Matching Algorithm Modeled By DSP Builder," Journal of Computers vol. 9, no. 10, pp. 2359-2364, 2014.