Department of Electronics, Farhat Abbass University in Setif, Setif, Algeria. Department of Computer Science, Mohamed Boudhiaf university, M’sila, Algeria.

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Abstract—High Level synthesis (HLS) tools are now attracting much the attention of hardware developers. Their high rates of productivity compared to hand hardware description language (HDL) coding are quite proved. In this paper much attention is accorded to the quality feature of HLS tools and we propose a total novel approach for building high quality HLS tools and an associate framework. We illustrate how the proposed policy is certifying upper quality where both speedup and throughput are ultimately improved. Those qualities are very interesting when target application is subjected to rigid time constraints and they were been ensured within the proposed tool through full exploration of intrinsic parallelism. We were guided to consider a data-flow programming paradigm where programs are transposed towards a novel representation form that has a parallel-spatial consistency. This paradigm is enabling an efficient and rigorous investigation of some important issues like Design Space Exploration, load balancing, task management and co-design challenges. We have been able to generate a soft core for the Advanced Encryption Standard (AES) cipher treated as a case study using the proposed tool. We reached 29.44 Gbps of throughput and 360 ns of latency at 230 MHz of functioning frequency which proves the validity of our approach for conducting best qualities solutions.

Index Terms—Hardware description languages, high level synthesis, high performance computing, parallel architectures, parallel processing, reconfigurable architectures.

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Cite: Aimad Eddine Debbi, "Data-Flow Programming Paradigm for High Level Synthesis Improvement," Journal of Computers vol. 13, no. 6, pp. 622-637, 2018.