Volume 13 Number 5 (May 2018)
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JCP 2018 Vol.13(5): 555-563 ISSN: 1796-203X
doi: 10.17706/jcp.13.5.555-563

Exploring Multi-core Design Space: Heracles vs. Rocket Chip Generator

Eduardo André Neves, Samuel Xavier-de-Souza
Department of Computer Engineering and Automation Federal University of Rio Grande do Norte, Natal, RN, Brazil.
Abstract—This article presents the analysis and comparison of two powerful tools to explore design space and study multi-core microprocessors. Heracles, developed at the MIT, is a modular tool to create MIPS multi-core processors. Its modularity allows quick development by varying the types of processor, memory, network interconnect and cache. RISC-V is a new instruction set architecture, developed at the University of California, Berkeley, that has several tools for designing architectures and processors that use this instruction set. The Rocket Chip Generator is one of these tools. It is the equivalent of Heracles for the MIPS architecture and, as such, provide several features that allows rapid development of RISC-V multi-core processors. We compared the target hardware and software features of these tools. The Rocket Chip Generator proved to be an excellent tool for the development of new RISC-V processors whereas Heracles seemed a more adequate tool for teaching and parallel architecture research at higher levels of abstraction.

Index Terms—Design space exploration, multi-core, heracles, rocket chip generator, MIPS, RISC-V.

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Cite: Eduardo André Neves, Samuel Xavier-de-Souza, "Exploring Multi-core Design Space: Heracles vs. Rocket Chip Generator," Journal of Computers vol. 13, no. 5, pp. 555-563, 2018.

General Information

ISSN: 1796-203X
Frequency: Monthly (2006-2014); Bimonthly (Since 2015)
Editor-in-Chief: Prof. Liansheng Tan
Executive Editor: Ms. Nina Lee
Abstracting/ Indexing: DBLP, EBSCO, DOAJ, ProQuest, INSPEC, ULRICH's Periodicals Directory, WorldCat, CNKI,etc
E-mail: jcp@iap.org
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