Department of Electronics College of Technology at Alkharj, Saudi Arabia.

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Abstract—In this paper, we present a novel temporal partitioning methodology for dynamically reconfigurable computing systems to reduce the communication costs of the design. This aim can be reached by minimizing the transfer of data required between design partitions. Our algorithm use the network flow-based multi-way task partitioning algorithm to minimize communication costs for temporal partitioning.. The proposed methodology was tested on several examples on the Xilinx Virtex-II pro. The results show significant reduction in the communication cost compared with others famous approaches used in this field.

Index Terms—Temporal partitioning, dynamically reconfigurable architectures, communication costs, FPGA.

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Cite: Abdo Azibi, Ramzi Ayadi, Med Lassaad Kaddachi, "An Enhanced Network Flow Algorithm for Temporal Partitioning into Reconfigurable Architectures," Journal of Computers vol. 10, no. 3, pp. 176-183, 2015.