Department of Computer Science and Technology, Tongji University, Shanghai, China

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Abstract—As chip feature size decreases, processors are getting more and more sensitive to soft errors. To find cheaper reliability solutions has attracted the attention of many researches. SMT (Simultaneous Multithreading) processor permits multiple issues from different threads at the same time, which provides nature support for faulttolerance by executing threads redundantly. Many RMT (Redundant Multithreading) architectures have been proposed. In those architectures, IQ (Instruction Queue) is a critical resource that affects the performance obviously. This paper proposed DDDI (Delay Dispatching Dependent Instructions) strategy which can use IQ more efficiently. In DDDI, instructions that dependent on load instructions that encounter cache miss can't be dispatched in to IQ until the load instructions get values from L2 cache or main memory. Experiments show that DDDI can avoid the threads that encounter cache miss blocking IQ resources, and not only IQ, but also the whole pipeline can be used more efficiently. Performance is boosted outstandingly.

Index Terms—Instruction Queue, SRT, cache miss, RMT, rename register file

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Cite: Jie Yin, Jianhui Jiang, "Easing Instruction Queue Competition among Threads in RMT," Journal of Computers vol. 6, no. 7, pp. 1394-1401, 2011.