Volume 5 Number 10 (Oct. 2010)
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JCP 2010 Vol.5(10): 1494-1501 ISSN: 1796-203X
doi: 10.4304/jcp.5.10.1494-1501

Digital High Order Multiplier-free Delta Sigma Modulator for Multistandard Fractional-N Frequency Synthesizer

Manel Ben-Romdhane, Aymen Abeda, and Chiheb Rebai
CIRTA'COM Research Lab. Ecole Supérieure des Communications de Tunis SUP'COM Cité Technologique des Communications, Ariana, Tunisie

Abstract—This paper proposes a new stable design strategy for 1- bit high order digital DS modulator for multistandard fractional- N frequency synthesizer. The proposed digital DS modulator presents simplicity, low power consumption and controls a dualmodulus divider instead of multi-modulus one as in existing DS fractional-N frequency synthesizer. Simulation results illustrate the DS modulator good performances in terms of spectrum purity and accuracy. Using this stable 1-bit digital DS modulator output to a fractional-N frequency synthesizer Simulink model verifies the multistandard frequency synthesizer specifications.

Index Terms—TMultistandard frequency synthesis, Fractional-N PLL, Digital DS modulator.

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Cite: Manel Ben-Romdhane, Aymen Abeda, and Chiheb Rebai, " Digital High Order Multiplier-free Delta Sigma Modulator for Multistandard Fractional-N Frequency Synthesizer," Journal of Computers vol. 5, no. 10, pp. 1494-1501, 2010.

General Information

ISSN: 1796-203X
Abbreviated Title: J.Comput.
Frequency: Monthly
Editor-in-Chief: Prof. Liansheng Tan
Executive Editor: Ms. Nina Lee
Abstracting/ Indexing: DBLP, EBSCO,  ProQuest, INSPEC, ULRICH's Periodicals Directory, WorldCat, CNKI,etc
E-mail: jcp@iap.org
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