¹ School of Computer, National University of Defense Technology, Changsha 410073, Hunan, China
² School of Computer Science, University of Birmingham, Edgbaston, Birmingham, B15 2TT, United Kingdom

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Abstract—Virtual Machine (VM) can not only release the processor designers from the burden of ensuring crossplatform compatibility but also provide new opportunities for innovation. Instruction Set Architecture (ISA) emulation is the key aspect of a VM. This paper describes the design and implementation of TransARM-IU, a use-level ISA emulator that supports IA-32 applications on ARMbased systems. This paper also discusses several dedicated solutions to several crucial issues related to the development of TransARM-IU, such as the Executable and Linking Format resolution and hybrid threaded interpretation. In particular, conventional interpretation is implemented in a centralized style which consumes much more execution time. A hybrid threaded interpretation method is proposed to improve the efficiency of the emulator by appending a portion of the simple decoding and dispatching code to the end of each of the instruction interpreter routines. For performance evaluation, we selected 6 benchmarks from MiBench and carried out the experiments on two real ARM-based systems. Experimental results demonstrate the correctness of TransARM-IU in terms of ISA emulation and indicate that TransARM-IU is competitive to other ISA emulators.

Index Terms—virtualization, interpretation, emulation

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Cite: Wei Chen, Zhiying Wang, and Dan Chen, " An Emulator for Executing IA-32 Applications on ARM-Based Systems," Journal of Computers vol. 5, no. 7, pp. 1133-1141, 2010.