School of Mechanical Engineering, Hubei University of Technology, Wuhan, 430068, China

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Abstract—This article described a complete design of parallel interface based on ARM & FPGA, using the on-chip DPRAM in FPGA to improve the metastability problem which was generated during data transmission between the asynchronous clock-domains; And it achieved the design of ARM & FPGA hardware interface module, data-sending module, data-receiving module and FPGA driver module, also gave the feasible method that using a flag to solve the dislocation of data-reading; Test results indicate that the system works steadily.

Index Terms—ARM, FPGA, Parallel Data Interface, metastability.

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Cite: Daode Zhang, Yurong Pan, Xinyu Hu, "Design of High-Speed Parallel Data Interface Based on ARM & FPGA," Journal of Computers vol. 7, no. 3, pp. 804-809, 2012.