Volume 5 Number 3 (Mar. 2010)
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JCP 2010 Vol.5(3): 471-478 ISSN: 1796-203X
doi: 10.4304/jcp.5.3.471-478

An Intelligent Multi-Port Memory

Zuo Wang
School of Computer Science and Technology, Beijing Institute of Technology, Beijing, China

Abstract—It has become clear that on-chip storage is critical in large FPGAs. Scholars have done some researches on implementing user logic memory models with single-port and dual-port physical arrays. Their work is based on the assumption that user memory models are either single-port or dual-port. However, their works may not be helpful to multi-processor applications since single or dual-port arrays may not satisfy the simultaneous accesses from different processors. This paper proposes a novel multi-port memory design. In our design, distributed memory resources of LUT are mapped as 1-port memory banks. Data in different memory banks can be accessed simultaneously. With the help of port-priority and r/w-priority, our multi-port memory can resolve both write-write conflict and read-write conflict. When write-write conflict occurs, the port with the highest priority can execute its write operation. When readwrite conflict occurs, either read-then-write or write-thenread type is selected according to r/w-priority. Besides, dataswitch paths between ports are implemented by utilizing the read-write conflict. Extend Port Importance Hierarchy (EPIH) algorithm is proposed for basic conflict handling, while Block Access Control (BAC) algorithm is proposed for reducing conflict when processors carry block read/write. Experiment results on Xilinx Virtex-II show that: compared to implementation of N ports in each cell, our design saves 88% LUT resources. Experiment results on Xilinx Virtex-II also show that, as port number N increases, the cell cost increases significantly which restricts the reasonable port number to rather small values in practice. Experiment results on simulation show that BAC algorithm performs more efficiently according to increasing block read/write length.

Index Terms—FPGA, N-port memory, mapping, hierarchy, embedded arrays


Cite: Zuo Wang, " An Intelligent Multi-Port Memory," Journal of Computers vol. 5, no. 3, pp. 471-478, 2010.

General Information

ISSN: 1796-203X
Abbreviated Title: J.Comput.
Frequency: Bimonthly
Editor-in-Chief: Prof. Liansheng Tan
Executive Editor: Ms. Nina Lee
Abstracting/ Indexing: DBLP, EBSCO,  ProQuest, INSPEC, ULRICH's Periodicals Directory, WorldCat,etc
E-mail: jcp@iap.org
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