JCP 2010 Vol.5(3): 337-344 ISSN: 1796-203X
doi: 10.4304/jcp.5.3.337-344
doi: 10.4304/jcp.5.3.337-344
The Influence of the Nanometer Technology on Performance of CPL Full Adders
Abdoul M. Rjoub and AL-Mamoon Al-Othman
Jordan University of Science and Technology Department of Computer Engineering Irbid 22110, P. O. Box 3030, Jordan
Abstract—In this paper the performance of 8-transistor based Full adder is analyzed, evaluated, and compared with that of three different types of Full Adders based on Complementary Pass Transistor XOR Logic gate. Simulation results using nano-scale SPICE parameters are obtained for the above mentioned FAs. It is shown that the performance of the 8-transistor based Full adder in term of power dissipation is superior to that of the other FAs. Multi- Supply Voltage Technique is used to optimize the outputs of 8-Transistor Full Adder. A new technique based on minimum leakage vector is proposed to reduce the leakage current when the circuit is in its off state.
Index Terms—Full Adder, Minimum Leakage Vector, Multi-Supply Voltage, Nano-Technology, Pass Transistor Logic, XOR logic gate.
Abstract—In this paper the performance of 8-transistor based Full adder is analyzed, evaluated, and compared with that of three different types of Full Adders based on Complementary Pass Transistor XOR Logic gate. Simulation results using nano-scale SPICE parameters are obtained for the above mentioned FAs. It is shown that the performance of the 8-transistor based Full adder in term of power dissipation is superior to that of the other FAs. Multi- Supply Voltage Technique is used to optimize the outputs of 8-Transistor Full Adder. A new technique based on minimum leakage vector is proposed to reduce the leakage current when the circuit is in its off state.
Index Terms—Full Adder, Minimum Leakage Vector, Multi-Supply Voltage, Nano-Technology, Pass Transistor Logic, XOR logic gate.
Cite: Abdoul M. Rjoub and AL-Mamoon Al-Othman, " The Influence of the Nanometer Technology on Performance of CPL Full Adders," Journal of Computers vol. 5, no. 3, pp. 337-344, 2010.
General Information
ISSN: 1796-203X
Abbreviated Title: J.Comput.
Frequency: Bimonthly
Abbreviated Title: J.Comput.
Frequency: Bimonthly
Editor-in-Chief: Prof. Liansheng Tan
Executive Editor: Ms. Nina Lee
Abstracting/ Indexing: DBLP, EBSCO, ProQuest, INSPEC, ULRICH's Periodicals Directory, WorldCat,etc
E-mail: jcp@iap.org
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