Volume 4 Number 2 (Feb. 2009)
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JCP 2009 Vol.4(2): 119-126 ISSN: 1796-203X
doi: 10.4304/jcp.4.2.119-126

Two New Low-Power and High-Performance Full Adders

Mohammad Hossein Moaiyeri1, Reza Faghih Mirzaee1, Keivan Navi2
1Department of Computer Engineering, Science and Research Branch of Islamic Azad University, Tehran, Iran
2Faculty of Electrical and Computer Engineering, Shahid Beheshti University, GC, Tehran, Iran


Abstract—Two new low-power, and high-performance 1- bit Full Adder cells are proposed in this paper. These cells are based on low-power XOR/XNOR circuit and Majority-not gate. Majority-not gate, which produces Cout (Output Carry), is implemented with an efficient method, using input capacitors and a static CMOS inverter. This kind of implementation benefits from low power consumption, a high degree of regularity and simplicity. Eight state-of-the-art 1-bit Full Adders and two proposed Full Adders are simulated with HSPICE using 0.18μm CMOS technology at several supply voltages ranging from 2.4v down to 0.8v. Although low power consumption is targeted in implementation of our designs, simulation results demonstrate great improvement in terms of power consumption and also PDP.

Index Terms—Full Adder Cell, Majority-not Gate, Low- Power, High-Performance, Power-Delay Product.

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Cite: Mohammad Hossein Moaiyeri, Reza Faghih Mirzaee, Keivan Navi, "Two New Low-Power and High-Performance Full Adders," Journal of Computers vol. 4, no. 2, pp. 119-126, 2009.

General Information

ISSN: 1796-203X
Abbreviated Title: J.Comput.
Frequency: Monthly
Editor-in-Chief: Prof. Liansheng Tan
Executive Editor: Ms. Nina Lee
Abstracting/ Indexing: DBLP, EBSCO,  ProQuest, INSPEC, ULRICH's Periodicals Directory, WorldCat, CNKI,etc
E-mail: jcp@iap.org
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