Volume 4 Number 7 (Jul. 2009)
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JCP 2009 Vol.4(7): 567-575 ISSN: 1796-203X
doi: 10.4304/jcp.4.7.567-575

A High Density and Low Power Cache Based on Novel SRAM Cell

Arash Azizi Mazreah1, Mohammad Taghi Manzuri2, Ali Mehrparvar3
1Islamic Azad University, Science and Research Branch, and Islamic Azad University, Sirjan Branch
2Sharif University of Technology
3Islamic Azad University, Arak Branch


Abstract—Based on the observation that dynamic occurrence of zeros in the cache access stream and cacheresident memory values of ordinary programs exhibit a strong bias towards zero, this paper presents a novel CMOS five-transistor SRAM cell (5T SRAM cell) for very high density and low power cache applications. This cell retains its data with leakage current and positive feedback without refresh cycle. Novel 5T SRAM cell uses one word-line and one bit-line and extra read-line control. The new cell size is 17% smaller than a conventional six-transistor SRAM cell using same design rules with no performance degradation. Simulation and analytical results show purposed cell has correct operation during read/write and also the average dynamic energy consumption of new cell is 30% smaller than a six-transistor SRAM cell.

Index Terms—5T SRAM cell, Read static noise margin free, Cell current, Cell leakage, Cell area, dynamic energy consumption.

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Cite: Arash Azizi Mazreah, Mohammad Taghi Manzuri, Ali Mehrparvar, "A High Density and Low Power Cache Based on Novel SRAM Cell," Journal of Computers vol. 4, no. 7, pp. 567-575, 2009.

General Information

ISSN: 1796-203X
Abbreviated Title: J.Comput.
Frequency: Monthly
Editor-in-Chief: Prof. Liansheng Tan
Executive Editor: Ms. Nina Lee
Abstracting/ Indexing: DBLP, EBSCO,  ProQuest, INSPEC, ULRICH's Periodicals Directory, WorldCat, CNKI,etc
E-mail: jcp@iap.org
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